A standard 24-transistor implementation of a static 1-bit full

Comprehensive study of 1-Bit full adder cells: review, performance comparison and scalability analysis

How to realize F=(AB+ACE+CD+DBE)' using CMOS with the minimum number of transistors - Quora

Logic gate - Wikipedia

A Novel High-Performance Hybrid Full Adder for VLSI Circuits

Design and analysis of hybrid 10T adder for low power applications - ScienceDirect

A standard 24-transistor implementation of a static 1-bit full adder

1 bit full adder made using Transistors : r/logisim

Comparative Study of CMOS Full Adder Logic Styles

Karnaugh maps for Boolean function F2 and corresponding standard